Data Sheet
ADM4210
Rev. A | Page 5 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ON
IMER 1
GND 2
3
V
CC
6
GATE
4
SENSE
5
ADM4210-1AUJ
TOP VIEW
(Not to Scale)
Figure 3. Pin Configuration, 1AUJ Model
N-CLR
TIMER 1
GND 2
3
V
CC
6
GATE
4
SENSE
5
ADM4210-2AUJ
TOP VIEW
(Not to Scale)
Figure 4. Pin Configuration, 2AUJ Model
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
TIMER
Timer Input Pin. The initial and circuit breaker timing cycles are set by this external capacitor. The initial timing
delay is 272.9 ms/糉, and 21.7 ms/礔 for a circuit breaker delay. When the TIMER pin is pulled beyond the upper
threshold, the GATE turns off.
2
GND
Chip Ground Pin.
3
ON (ON-CLR
) Input Pin. The ON (ON-CLR
) pin is an input to a comparator that has a low-to-high threshold of 1.3 V with 80 mV
hysteresis and a glitch filter. The ADM4210 is reset when the ON (ON-CLR
) pin is low. When the ON (ON-
CLR
) pin is
high, the ADM4210 is enabled. A rising edge on this pin has the added function of clearing a fault and restarting
the device on the latched off model, the ADM4210-2.
4
GATE
Gate Output Pin. An internal charge pump provides a 12 礎 pull-up current to drive the gate of an N-channel
MOSFET. In an overcurrent condition, the ADM4210 controls the external FET to maintain a constant load
current.
5
SENSE
Current Limit Sense Input Pin. The current limit is set via a sense resistor between the V
CC
and SENSE pins. In an
overcurrent condition, the gate of the FET is controlled to maintain the SENSE voltage at 50 mV. When this limit is
reached, the TIMER circuit breaker mode is activated. The circuit breaker limit can be disabled by connecting the
VCC pin and SENSE pin together.
6
VCC
Positive Supply Input Pin. The ADM4210 operates between 2.7 V to 16.5 V. An undervoltage lockout (UVLO)
circuit with a glitch filter resets the ADM4210 when the supply voltage drops below the specified UVLO limit.
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